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Wednesday, April 6 • 2:00pm - 4:30pm
A Lightweight Early Arbitration Method for Low-Latency Asynchronous 2D-Mesh NoC’s [P12]

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The thrust of massively-parallel computing has become the dominating trend in the micro-electronics industry over the last decade. An efficient on-chip communication infrastructure is a key to building such high-performance many-core processors. In recent years, networks-on-chip (NoC’s) are identified as a promising solution to resolve the on-chip-communication bottleneck. These on-chip networks replace traditional ad hoc bus-based communication with packet switching in a structured network architecture, and therefore inherently separate the design of communication from computing elements. A new low-latency interconnection network, "AEoLiAN," is proposed, using a 2D mesh topology. An asynchronous (i.e. clock-less) design methodology is used to obtain high-performance and ease-of-integration heterogeneous processors. The NoC contains a lightweight monitoring network to rapidly notify routers of incoming traffic in advance, thereby allowing early arbitration and channel allocation. Network-level simulations show significant improvements in system latency (34.4-37.9%) and moderate throughput gain (14.7-27.1%) over an existing optimized asynchronous baseline network.

Demo/Poster Presenter
avatar for Weiwei Jiang

Weiwei Jiang

PhD Candidate in Computer Science, Columbia Engineering
Weiwei Jiang is a Ph.D. candidate in the Department of Computer Science at Columbia University, working with Prof. Steven Nowick. He received the M.S. degree in computer science from Columbia University in 2010 and the B.S. degree from Tsinghua University, China in 2008, with a concentration... Read More →

Wednesday April 6, 2016 2:00pm - 4:30pm EDT
Roone Arledge Auditorium Lerner Hall, Columbia University 2920 Broadway, New York, NY 10040