Data Science Day @ Columbia University

The thrust of massively-parallel computing has become the dominating trend in the micro-electronics industry over the last decade. An efficient on-chip communication infrastructure is a key to building such high-performance many-core processors. In recent years, networks-on-chip (NoC’s) are identified as a promising solution to resolve the on-chip-communication bottleneck. These on-chip networks replace traditional ad hoc bus-based communication with packet switching in a structured network architecture, and therefore inherently separate the design of communication from computing elements. A new low-latency interconnection network, "AEoLiAN," is proposed, using a 2D mesh topology. An asynchronous (i.e. clock-less) design methodology is used to obtain high-performance and ease-of-integration heterogeneous processors. The NoC contains a lightweight monitoring network to rapidly notify routers of incoming traffic in advance, thereby allowing early arbitration and channel allocation. Network-level simulations show significant improvements in system latency (34.4-37.9%) and moderate throughput gain (14.7-27.1%) over an existing optimized asynchronous baseline network.