Data Science Day @ Columbia University

In the on-going quest to enabling energy-efficient cognitive computing, specialized, often non-Von-Neumann, architecture in near/sub-VTH circuits emerges as a promising candidate. However, the complex and parallel nature of the architecture combined with the large delay variability from near/sub-VTH circuits impose prohibitive timing margin to cycle time and limit the achievable efficiency. The conventional error detection and correction (EDAC) techniques can remove margin, however, they can cause significant overhead since most of them target super-VTH in-order microprocessors. In this work, EDAC technique suitable for near/sub-VTH complex and parallel architecture is demonstrated in an unsupervised sorter based on spiking neural network for brain-computer-interface microsystems using 1) body boost correction, 2) fully-static error-detecting latch, 3) sparse error detection, and 4) local-buffer-less latches and clock distribution. The technique improves energy-efficiency by 49.3% and FCLK by 35.6% compared to the baseline with margin at the area overhead of 4.1%. No additional VDD is needed.